Field of the Invention
The present invention relates to FIFO (First In First Out) buffers used for signal processing, and more particularly relates to the optical FIFO buffers used for optical signal processing, for example, optical computing, optical packet switching and the like.
Prior Art
Recently, optical technology has been introduced into signal processing performed in various fields, for example, communications, computing, packet switching and the like, the performance of which is thereby greatly improved.
In these signal processings, the case is often encountered in which a processing system cannot accept incoming signals continuously supplied from other devices connected thereto. In addition, a signal collision in which two different signals are simultaneously supplied to the same node may occur, whereby the functions to be achieved by the respective signals cannot be achieved. In order to prevent these problems, the input timing at which signals are supplied to the processing system must be controlled based on the current state of the processing system. For this reason, delay operations or buffering operations are used for various signal processing systems.
FIG. 12 shows an example of a conventional delay circuit using optical fiber delay lines. In FIG. 12, CA.sub.0 through CA.sub.n-1 respectively designate 2.times.2 optical couplers. To these 2.times.2 optical couplers CA.sub.0 through CA.sub.n-1, fiber delay lines LA.sub.0 through LA.sub.n-1 are respectively connected, wherein the fiber delay lines LA.sub.0 through LA.sub.n-1 respectively have propagation delay times 2.sup.0 T through 2.sup.n-1 T (T is a constant). In addition, to the 2.times.2 optical coupler CA.sub.0 through CA.sub.n-1, delay designation signals X.sub.0 through X.sub.n-1 are respectively supplied. In the case where the delay designation signal X.sub.i is active, a signal which comes into the 2.times.2 optical coupler CA.sub.i is delayed by passing through the fiber delay line LA.sub.i, after which the delayed signal is outputted from the 2.times.2 optical coupler CA.sub.i. In contrast, in the case where the delay designation signal X.sub.i is not active, a signal which comes into the 2.times.2 optical coupler CA.sub.i is directly outputted without passing through the fiber delay line LA.sub.i. With this delay circuit, the input timing at which signals are supplied to the processing system can be controlled among (2.sup.n -1 )T through 0 based on the delay designation signals X.sub.0 through X.sub.n-1.
By using a configuration similar to that shown in FIG. 12, a FIFO buffer can be constituted as shown in FIG. 13. In FIG. 13, CB.sub.0 through CB.sub.n-1 respectively designate 2.times.2 optical switches, wherein the 2.times.2 optical switches CB.sub.0 through CB.sub.n-1 are connected together in a cascade manner. To these 2.times.2 optical couplers CB.sub.0 through CB.sub.n-1, fiber delay lines LB.sub.0 through LB.sub.n-1 are respectively connected, wherein the fiber delay lines LB.sub.0 through LB.sub.n-1 have the same propagation delay time. Each 2.times.2 optical switch CB.sub.i and fiber delay line LB.sub.i connected therewith constitute a fiber loop memory for holding an optical signal which comes thereto. New incoming signals are sequentially supplied to the input terminal of the first stage 2.times.2 optical switch CB.sub.n-1 which is inserted in the first stage fiber loop memory. The output signals are picked up from the last stage 2.times.2 optical switch CB.sub.0 inserted in the last stage fiber loop memory, after the output signals are sequentially supplied to a device connected to the FIFO buffer. Hereinafter, a device which accepts the signals supplied from the FIFO buffer will be called a "continued device". A control unit (not shown) usually monitors the status of respective stage fiber loop memories and the status of the continued device. Based on the detected status, the control unit supplies traffic control signals Y.sub.0 through Y.sub.n-1 respectively to the 2.times.2 optical switches CB.sub.0 through CB.sub.n-1, whereby the input/output operation and holding operation of each fiber loop memory is controlled. By this control, the new incoming signal automatically propagates through the fiber loop memories which hold no signals, after which the incoming signal is automatically held in the fiber loop memory which is the nearest stage to the last stage and holds no signal. In addition, when the continued device can accept signals, the signal held in the last stage fiber loop memory is picked up from the 2.times.2 optical switch CB.sub.n-1, after which the picked up signal is supplied to the continued device. In the above-described FIFO buffer, the operations of respective portions provided in the FIFO buffer are controlled by the control unit in an integrated manner, the signals are automatically held and pass through the FIFO buffer, after which the signals are supplied to the continued device at the preferable timing at which the continued device can accept and process the incoming signals. However, a problem occurs in that the timing control in which the control unit supplies the traffic control signals is extremely critical so that normal signal traffic cannot be obtained in the FIFO buffer without exact timing adjustment.